Del 08-05-2018 al 09-08-2019

High Level Synthesis using Vivado-HLS at ETHZ

Hands-on Intro to High Level Synthesis using Vivado-HLS

Class 1 :

Introduction to High-Level Synthesis (HLS). How is HW extracted from C dode, scheduling and binding, C Functions and RTL hierarchy, operators, loops, arrays in C, Validation flow.

Using Vivado HLS. Vivado HLS GUI mode, projects, synthesis, IP-XACT flow, design analysis, TCL in Vivado

Lab 1: Creating Project and Understanding Reports

Improving Performance. Use of directives. Improve latency manipulating loops: unrolling, flattening, and merging. Improving thoughput: Dataflow and Pipelining. Performance bottlenecks. Array partitioning and reshaping

Lab 2: Optimizing Performance through Pipelining

Class 2 :

Data Types: standard C/C++ and Arbitrary precision data types. Fixed and floating point (half-, single- and double-precision) data types

Improving Area and Resources Utilization. Limit number and select resources, mapping arrays, use of arbitrary precisions.

Lab 3: Improving Area and Resources Utilization

Block- and Ports- Level Protocols. How interface with the outside world. Block level protocols, IP adapters (AXI4, AXI4LiteS and AXI4Stream), port level handshakings.

Lab 4: Reviewing previous concept using a simple example.

Prerequisites:

Basic knowledge in C/C++ language, Digital design principles (RTL level), Notions of VHDL or Verilog are welcome.

Setup: Vivado-HLS 2017.2 or 2017.4. Webpack edition it is enough. We provide a Linux Virtual machine with tools installed (40-60 GB)

Dates and Place:

ETH Zürich. May 8-9, 2018

Galería de imágenes

Profesores a cargo:

Gustavo Sutter
Doctor en informática y telecomunicaciones por la Universidad Autónoma de Madrid, Ingeniero en Sistemas en la Univ. Nacional del Centro de la Prov. de Buenos Aires en Argentina. Cuenta con más de 15 años de experiencia en diseño de sistemas...Leer Más